A known approach for forming epitaxially grown silicon germanium (eSiGe) S/D regions for both planar and FinFET devices is illustrated in FIGS. 1, 2A, 2B, 2C, and 3. Adverting to FIG. 1, shallow trench isolation (STI) structures 101 are formed on opposite sides of a silicon (Si) substrate 103. A gate structure 105 is formed between the STI structures 101 on the Si substrate 103. Sigma-shaped cavities 201, box-shaped cavities 221, or ball-shaped cavities 231 are then formed in the Si substrate 103 by etching, as depicted in the FIGS. 2A, 2B, and 2C, respectively. Since SiGe does not grow on the STI dielectric, incomplete eSiGe S/D regions 301 are formed in the ball-shaped cavities 231, for example, as depicted in FIG. 3.
Another known approach for forming eSiGe S/D regions for both planar and FinFET devices is illustrated in FIGS. 4A through 7B. Adverting to FIGS. 4A and 4B (FIG. 4A is a top view and FIG. 4B is a cross-sectional view along the line 4B-4B′), a STI etch mask 401 is formed, for example, of nitride, over a Si substrate 403. STI deep trenches 405 are then formed in the Si substrate 403. An organic planarization layer (OPL) 501 is formed over the STI etch mask 401, filling the STI deep trenches 405, as depicted in FIG. 5B (FIG. 5A is a top view and FIG. 5B is a cross-sectional view along the line 5B-5B′). A silicon-containing anti-reflective coating (SiARC) layer 503 is then formed over the OPL layer 501. Next, a photoresist layer 505 is formed over the SiARC layer 503, as depicted in FIG. 5A. The photoresist layer 505 is formed with openings 507 over the now filled STI deep trenches 405. The openings 507 are formed slightly wider than the width of the STI deep trenches 405.
Adverting to FIGS. 6A and 6B (FIG. 6A is a top view and FIG. 6B is a cross-sectional view along the line 6B-6B′), the SiARC layer 503, the OPL layer 501, the STI etch mask 401, and a portion of the Si substrate 403 are then etched through openings 507 in the photoresist layer 505 to form shallow trenches 601. Then, the photoresist layer 505 and the SiARC layer 503 are removed. Next, the OPL layer 501 is removed, as depicted in FIGS. 7A and 7B. FIG. 7A is a top view and FIG. 7B is a cross-sectional view along the line 7B-7B′. A STI oxide layer 701 is then formed over the STI etch mask 401, filling the shallow trenches 601 and STI deep trenches 405. Thereafter, the STI oxide layer 701 is planarized, e.g., by chemical mechanical polishing (CMP), down to the STI etch mask 401. Consequently, a portion of the STI oxide layer 701 extends over the Si substrate 403 and, therefore, protects the Si substrate 403 underneath from etching. The extended portion of the STI oxide layer 701 enables the preserved Si to function as a seed layer for subsequent formation of the eSiGe S/D regions. However, this known approach requires an extra masking step and lithography, which increases overall processing costs.
A need therefore exists for methodology enabling the preservation of Si adjacent STI regions for subsequent epitaxial growth of complete S/D regions and the resulting device.